In semiconductor fabrication processes, a single layer of features is sometimes formed by using multiple-exposure or multiple-patterning to improve a spatial resolution of the particular layer. For example, in a method known as double patterning technology (DPT), layout patterns corresponding to a layout design for a particular layer of features are assigned to two different masks. The pattern-assigning process is sometimes also referred to as a “layout decomposition process,” and the pattern-assigning result is sometimes also referred to as a “layout decomposition result.” Performance of a pattern-assigning process on a layout design is usually computational resource demanding and time consuming.